The invention relates to an ultra fast logic circuitry, particularly for digital systems requiring extremely fast and complex digital processing, such as microprocessors.
Conventional high speed logic devices are supplied from a supply voltage which is significantly higher than the necessary logic voltage swing. The supply voltage is stabilized and uniform. Very critical are supply voltage ripples which may cause an erroneous operation of the logic components. However, a very noisy supply voltage is inevitable in complex systems. Temperature variations cause a shift of any input threshold level and output voltage level. A temperature compensation, if any, is poor due to a high number of components being balanced. Biasing components contribute to an increased supply voltage and consume a substantial amount of power. An enlarged voltage swing is necessary to increase noise immunity. As a result, on-state collector or drain currents and power dissipation during signal transition period are high. Resistor values are increased to minimize power consumption. However, this causes substantial gate delays even with a relatively short connection length.
Power dissipation is increased whenever an output stage comprises an output transistor having the emitter or collector coupled via a resistor to the power supply rail. Such a pull-up or pull-down resistor requires a small resistance in order to compensate for unequal output rise and fall times. This results in an excessive power dissipation that is proportional to square of the voltage swing. The power dissipation of CMOS and BiCMOS technologies is low at low frequencies but rises dramatically near maximum switching frequency. However, most logic components operate continuously at high frequencies in high speed digital systems. Push-pull output stages are employed as to increase drive capabilities. Such output stages are typical of TTL, CMOS and BiCMOS--common and rather slow logic families. Emitter coupled logic (ECL) has the fastest switching rates and shortest propagation delays of any silicon technology. However, power consumption is very high and some ECL systems require liquid cooling. ECL circuits require a negative supply voltage and another voltage for a terminating resistor return. Current mode logic (CML) is obtained by eliminating the ECL output stage consisting of a transistor and a pull-down resistor. CML has higher speed and lower power consumption. However, a CML loaded gate may have significantly lower switching times due to reduced fan-out and interconnection driving capability. Noise induced on the power supply rail and applied to the input stage is rejected by a differential action thereof. However, the noise applied to the ECL output stage is not cancelled out.
The ECL and CML are based on a differential amplifier principle. Each gate includes a pair of transistors having emitters coupled to a resistor or current source. The collectors of the transistors are coupled to ground via separate resistors, wherein one transistor is conducting while the other transistor is cut off, i.e., at least two transistors are switched. However, the input signal is applied to only one transistor. The other transistor is used for biasing and is merely capable of providing a complementary output signal. This transistor and current source further demand separate reference voltages and temperature compensation. Up to three levels of series gating are employed for added speed. This requires even more reference voltages. In spite of the laborious biasing, the voltages representing logic levels strongly depend on temperature, supply voltage and individual characteristics of transistors. As a result, an enlarged voltage swing and overblown supply voltage are necessary. The power consumption is remarkably high.
Logic types based on gallium-arsenide (GaAs), in particular direct coupled FET logic (DCFL), offer a better performance at higher cost. The high speed of the GaAs parts is reduced in order to achieve a compatibility with silicon logic families. The speed further deteriorates with increased loads and distances. The GaAs devices usually dissipate a few times less power than comparable ECL devices. However, in real operating conditions the speed is just slightly higher over ECL, i.e., far below the capabilities of GaAs. Moreover, ECL offers significantly higher circuit density at a fraction of the cost.